- Work Location: District 03, Ho Chi Minh City
- Monthly Salary: 20,000,000~77,000,000VND
<Job Responsibilities>
With the specifications required by the customer as INPUT
Carry out specific design verification work using the following languages
**OUTPUT
Functional specifications (English)
Implementation specifications (English)
RTL (Verilog / SystemVerilog)
Verification strategy (English)
Verification item table (English)
Verification environment construction / verification scenario (System Verilog / SVA / UVM / C)
Verification environment manual (English)
Verification result report (English)
- Other tasks assigned by the manager
<Necessary Skill / Experience>
- Age: under 35
- Gender: Any
- More than 3 years of experience as an Engineer Leader in the semiconductor industry, having skills as follows;
*Front-end design and verification of ASIC
*RTL design by Verilog HDL/VHDL
*Design and verification using a general-purpose bus AMBA(AXI/AHB/APB)
*Assertion-Based Verification
- Technician who can do tasks by himself/herself
<Preferable Skill / Experience>
- English skill : Business level(overseas business trip, meeting with overseas engineers)
- Technical skills as below
Design and verification of ASIC ASIC-built-in CPU
Design and verification of high-speed interfaces such as PCI Express and USB
Random verification using SystemVerilog
Testbench building that applied verification methodology(UVM)
NOTICE:
Only shortlisted candidates will be approached by RGF's consultant. Your resumes will be recorded in our system, and you will receive our Job Introduction Auto-email with suitable jobs in the coming time. Please check your email regularly to get our vacant job. Thanks so much!